Drone SoC

D1

Intelligence at the edge of flight.

A purpose-built system-on-chip for autonomous drones and aerial robotics — combining real-time flight control, onboard AI inference, and sensor fusion in a 5W envelope.

Request Engineering Sample

Power envelope

5 W

AI TOPS

32 TOPS

Process node

4 nm

Flight control latency

<1 ms

This chip is currently in development and has not been released.

Specifications shown are target design goals. Products are not available for purchase or sampling at this time. Join the waitlist below to be notified when engineering samples become available.

Technical specifications

Compute

CPU cores
8× RSVC Edge cores
AI accelerator
32 TOPS neural engine
DSP
Dual real-time DSP cores

Sensor Fusion

IMU interfaces
4× SPI/I2C
Camera ISP
4K @ 120 fps
LiDAR interface
Native PCIe 5.0

Connectivity

Radio
Wi-Fi 7 + BT 5.4
Mesh networking
Sub-GHz swarm radio
GNSS
Multi-band GPS/GLONASS

Power

TDP
5 W peak
Idle
0.8 W
Power modes
7 adaptive states

Built for autonomous flight

Autonomous Navigation

Real-time obstacle avoidance and path planning with onboard AI — no cloud round-trip required.

Swarm Coordination

Sub-GHz mesh radio enables tight multi-drone coordination for search, mapping, and delivery fleets.

Computer Vision

4K ISP and 32 TOPS neural engine power real-time object detection, tracking, and scene understanding.

Benchmark comparison

Normalized performance index. Higher is better. Based on target design specifications.

AI inference efficiency

RSVC
100
Competitor A
61
Competitor B
54

Flight control latency

RSVC
100
Competitor A
72
Competitor B
65

Power efficiency (TOPS/W)

RSVC
100
Competitor A
58
Competitor B
49

Software ecosystem

RSVC-OSROS 2PX4ArduPilotOpenCVTensorFlow LiteLinux RTOS
RSVC-OS

RSVC-OS — The Rust-Based Autonomous Kernel

RSVC-OS is Revolution Silicon's open-source, Rust-based real-time operating system and kernel purpose-built for the D1 SoC. Written entirely in safe Rust, it eliminates whole classes of memory-safety vulnerabilities at the kernel level — critical for autonomous systems where a crash means a crash landing. The microkernel architecture enforces strict process isolation between flight control, AI inference, and sensor fusion tasks, with deterministic scheduling guarantees down to 50 µs.

Safe Rust kernel

Zero unsafe blocks in the core kernel. Memory safety enforced at compile time — no buffer overflows, no use-after-free, no null pointer dereferences in flight-critical code paths.

Hard real-time scheduler

Priority-ceiling protocol scheduler with deterministic 50 µs worst-case interrupt latency. Flight control tasks are guaranteed CPU time regardless of AI inference load.

Microkernel isolation

Flight control, AI inference, sensor fusion, and comms run in isolated address spaces. A fault in the vision pipeline cannot corrupt the flight controller — ever.

Async I/O runtime

Custom async executor optimized for embedded I/O — IMU polling, camera frames, LiDAR scans, and radio packets handled without blocking, with zero heap allocation in hot paths.

Verified boot chain

Cryptographically signed bootloader through to kernel and application images. Tamper-evident attestation for defense and commercial certification requirements.

Open source

RSVC-OS is MIT-licensed and fully open source. Drone OEMs can audit, fork, and extend the kernel — with upstream contributions from the Revolution Silicon team.

rsvc-os / kernel / flight_controller.rs
#[rsvc_task(priority = CRITICAL, deadline_us = 50)]
async fn flight_controller(ctx: FlightCtx) -> ! {
    let mut imu = ctx.imu.lock().await;
    let mut motors = ctx.motors.lock().await;

    loop {
        // Read IMU — guaranteed within 50 µs
        let attitude = imu.read_attitude().await;

        // PID control loop — no heap allocation
        let correction = pid_step(&attitude, &ctx.setpoint);

        // Write motor commands atomically
        motors.set_all(correction).await;

        // Yield to scheduler — next deadline in 50 µs
        rsvc_os::yield_task().await;
    }
}
RustKernel language
50 µsWorst-case latency
0Unsafe blocks (core)
MITLicense

Request a D1 engineering sample

Talk with our embedded platform team about D1 integration, BSP support, and validation kits.